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Simple
Fast
Efficient

Spiking Neural Networks are among the best hopes for the upcoming energy efficient, embedded Edge Artificial Intelligence. iSoC methodology ensures abstract, simulable, truly event-based SNN inference models that can be further designed and integrated in dedicated hardware accelerators very quickly through the use of High Level Synthesis tools.

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Simple
Fast
Efficient

Spiking Neural Networks are among the best hopes for the upcoming energy efficient, embedded Edge Artificial Intelligence. iSoC methodology ensures abstract, simulable, truly event-based SNN inference models that can be further designed and integrated in dedicated hardware accelerators very quickly through the use of High Level Synthesis tools.

Read More

Simple
Fast
Efficient

Spiking Neural Networks are among the best hopes for the upcoming energy efficient, embedded Edge Artificial Intelligence. iSoC methodology ensures abstract, simulable, truly event-based SNN inference models that can be further designed and integrated in dedicated hardware accelerators very quickly through the use of High Level Synthesis tools.

Read More
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News and documentation In-depth reading

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Online demonstrators Proofs of concept

Visual demonstrations of SNN inference IP cores fully operating on FPGA devices.Read More >

Download section IP cores

Download various SNN inference IP cores for free usage, experimentation and research.Read More >

About

30 décembre 2021
 |  Non classé

iSoC founder Sébastien Bilavarn received the B.S. and M.S. degrees from the University of Rennes in 1998 and the Ph.D. degree in Electrical Engineering from the University of South Brittany in 2002. Then he joined the Signal Processing Laboratories at the Swiss Federal Institute of Technology (EPFL) for a three year post-doc fellowship to conduct […]

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